Apart from the examples covered with full tutorials in the previous sections,
cocotb/examples/ contains some more smaller modules you may want to take a look at.
cocotb/examples/adder/ contains an
adder RTL in both Verilog and VHDL,
adder_model implemented in Python,
and the cocotb testbench with two defined tests a simple
a slightly more advanced
This example does not use any
Scoreboard; not even a clock.
cocotb/examples/dff/ contains a simple D flip-flop, implemented in both VDHL and Verilog.
The HDL has the data input port
d, the clock port
c, and the data output
q with an initial state of
No reset port exists.
The cocotb testbench checks the initial state first, then applies random data to the data input.
The flip-flop output is captured at each rising edge of the clock and compared to the applied input data using a
The testbench defines a
BitMonitor (a sub-class of
Monitor) as a pendant to the cocotb-provided
stop() methods are used
to start and stop generation of input data.
TestFactory is used to generate the random tests.
contains a module for multiplying two matrices together,
implemented in both VHDL and SystemVerilog.
The module takes two matrices
b_i as inputs
and provides the resulting matrix
c_o as an output.
On each rising clock edge,
c_o is calculated and output.
valid_i is high
c_o is calculated,
valid_o goes high to signal a valid output value.
The testbench defines
(both sub-classes of
and a test case
MatrixInMonitor watches for valid input matrices,
then does the multiplication in Python
and stores the result as the expected output matrix.
MatrixOutMonitor watches for valid output matrices
and compares the result to the expected value.
The testbench makes use of
and random data generators
to test many sets of matrices,
Scoreboard to compare expected and actual results.
The number of data bits for each entry in the matrices, as well as the row and column counts for each matrix, are configurable in the Makefile.
The example module uses one-dimensional arrays in the port definition to represent the matrices.
cocotb/examples/mean/ contains a module that calculates the mean value of a
data input bus
i (with signals
outputs it on
It has implementations in both VHDL and SystemVerilog.
The testbench defines a
StreamBusMonitor (a sub-class of
BusMonitor), a clock generator,
value_test helper coroutine and a few tests.
mean_randomised_test uses the
Scoreboard with the collected transactions on input bus
cocotb/examples/mixed_language/ contains two toplevel HDL files,
one in VHDL, one in SystemVerilog, that each instantiate the
SystemVerilog and VHDL in parallel and chains them together so that the endianness is swapped twice.
Thus, we end up with SystemVerilog+VHDL instantiated in VHDL and SystemVerilog+VHDL instantiated in SystemVerilog.
The cocotb testbench pulls the reset on both instances and checks that they behave the same.
AXI Lite Slave¶
cocotb/examples/axi_lite_slave/ contains …
This example with two different designs shows how cocotb can be used in an analog-mixed signal (AMS) simulation, provided your simulator supports this. Such an AMS setup involves a digital and an analog simulation kernel, and also provides means to transfer data between the digital and the analog domain.
The “-AMS” variants of the common digital HDLs (VHDL-AMS, Verilog-AMS and SystemVerilog-AMS) and languages like Spice can be used to express the analog behavior of your circuit.
Due to limitations of the underlying simulator interfaces (VPI, VHPI, FLI), cocotb cannot directly access the analog domain but has to resort to e.g. HDL helper code. Thus, unlike the other examples, part of this testbench is implemented with cocotb and the helper part with HDL.
- The cocotb
- The cocotb